1. Field of the Invention
The present invention relates to a solid-state image capturing apparatus, a manufacturing method of the solid-state image capturing apparatus, and an electronic information device. More particularly, the present invention relates to a solid-state image capturing apparatus that is capable of independently setting a concentration profile of a forming region of an amplifying transistor that constitutes a pixel from a concentration profile of a forming region of a transistor that constitutes a circuit around the pixel, a manufacturing method of such solid-state image capturing apparatus, and an electronic information device having the solid-state image capturing apparatus, such as a digital still camera, a digital video camera and a camera-equipped cell phone device.
2. Description of the Related Art
In recent years, a solid-state image capturing apparatus equipped with an amplifying MOS transistor (referred to as a MOS type solid-state image capturing apparatus, herein after) has become an attention in terms of its high sensitivity and the like. The MOS type solid-state image capturing apparatus includes a photodiode and a MOS transistor for each pixel, where the MOS transistor amplifies a signal detected by the photodiode.
A conventional MOS type solid-state image capturing apparatus will be described with reference to FIGS. 11 to 15. FIG. 11(a) is a plan view showing a diagrammatic structure of a conventional MOS type solid-state image capturing apparatus. As shown in FIG. 11(a), a MOS type solid-state image capturing apparatus 200 includes a pixel section 200a formed on a semiconductor substrate 100, and a peripheral circuit sections 201 and 202 formed in the periphery of the pixel section 200a of the semiconductor substrate. The pixel section 200a includes a plurality of pixels (see FIG. 11(b)), and the peripheral circuit sections 201 and 202 include a peripheral circuit for driving pixels.
FIG. 11(b) is a circuit diagram showing one example of a circuit structure of the conventional MOS type solid-state image capturing apparatus. As shown in FIG. 11(b), a plurality of pixels 1 are arranged in a matrix in the pixel section 200a of the MOS type solid-state image capturing apparatus 200.
Each pixel 1 includes a photodiode 3, a transfer transistor 4, an amplifying transistor 14, a reset transistor 15, and a vertical selection transistor 16. The photodiode 3 converts incident light into a signal charge and stores the signal charge. The transfer transistor 4 reads out the signal charge stored in the photodiode 3. The amplifying transistor 14 amplifies the signal charge that is read out by the transfer transistor 4 to convert the signal charge into a signal voltage, and then outputs the signal voltage. The reset transistor 15 resets the signal charge stored in the photodiode 3.
In addition, the peripheral circuit sections 201 and 202 in the MOS type solid-state image capturing apparatus 200 includes a vertical driving circuit 12, horizontal driving circuit 13, a load transistor group 17, and a row signal storing section 18. The vertical driving circuit 12 is connected to gates of the reset transistors 15 of respective horizontal lines via a plurality of reset transistor control lines 111. The reset transistor control lines 111 are arranged horizontally at a regular interval.
In addition, the vertical driving circuit 12 is connected to gates of the transfer transistors 4 for respective horizontal lines via a plurality of transfer transistor control line 131. The transfer transistor control lines 131 are arranged horizontally at a regular interval.
Further, the vertical driving circuit 12 is connected to gates of the vertical selection transistors 16 of respective horizontal lines via a plurality of vertical selection transistor control lines 121. The vertical driving circuit 12 selects a row to read out a signal via the vertical selection transistor control lines 121. Similar to the reset transistor control line 111, each of the vertical selection transistor control lines 121 are arranged horizontally at a regular interval.
The horizontal driving circuit 13 is connected to the row signal storing section 18. The row signal storing section 18 is equipped with a switching transistor for retrieving signals from each row. The row signal storing section 18 and the load transistor group 17 are connected to each other via a vertical signal line 161. Further, the row signal storing section 18 and the load transistor group 17 are connected to a source of the vertical selection transistor 16 via the vertical signal line 161 for every vertical line.
Next, an operation of the solid-state image capturing apparatus shown in FIG. 11 will be described.
First, when the electric potential of a predetermined vertical selection transistor control line 121 is turned to a high level by the vertical driving circuit 12 to select a predetermined row, the vertical selection transistor 16 on the selected row is turned on. In this stage, a source follower circuit is constituted by the amplifying transistor 14 and the load transistor group 17 on the selected row.
Next, when the electric potential of the reset transistor control line 111 on the selected row described above is turned to a high level while the vertical selection transistor 16 in the selected row is in an on-state, the reset transistor 15 on the selected row is turned on and the electric potential of a floating diffusion layer connected to the gate of the amplifying transistor in the selected row is reset.
After the reset transistor 15 on the selected row is turned off and when the electric potential of the transfer transistor control line 131 on the selected row is turned to a high level while the vertical selection transistor 16 is in an on-state, the transfer transistor 4 is turned on and the signal charge stored in the photodiode 3 is transferred to the floating diffusion layer.
In this stage, the gate voltage of the amplifying transistor 14 that is connected to the floating diffusion layer becomes equivalent to the electric potential of the floating diffusion layer, and the voltage of the vertical signal line is substantially equal to the gate voltage of the amplifying transistor 14. Thus, a signal based on the signal charge stored in the photodiode 3 is transferred to the row signal storing section 18.
Subsequently, while the vertical driving circuit 12 selects the next row, the horizontal driving circuit 13 successively outputs the voltage signal of each vertical signal line 161 to the row signal storing section 18. The row signal storing section 18 outputs the voltage signal from each vertical signal line 161 as an output signal to every row.
Next, a specific structure of the solid-state image capturing apparatus shown in FIG. 11 will be described with reference to FIGS. 12 and 13.
FIG. 12 is a plan view showing an enlarged pixel that constitutes the conventional solid-state image capturing apparatus shown in FIG. 11(b). FIG. 13 is a diagram showing a cross sectional structure of the pixel shown in FIG. 12, and more specifically, FIG. 13 shows a diagram of a cross section along the line A-B-C-D shown in FIG. 12. Note that a semiconductor substrate is omitted in FIG. 12.
As shown in FIG. 12, the photodiode 3 is equipped with an n-type semiconductor region 151 formed on the semiconductor substrate 100 (see FIG. 13). In the semiconductor substrate 100, an element separation section 92 is formed between adjacent semiconductor regions 151. In addition, a plurality of n-type semiconductor regions 5a to 5c are horizontally formed in a region adjacent to the semiconductor region 151 of the photodiode 3, with an element separation section 91 arranged therebetween. The semiconductor regions 5a to 5c are arranged vertically. Further, an n-type semiconductor region 154 is formed in a region vertically adjacent to the semiconductor region 151.
In addition, gate electrodes 153a and 153b are respectively formed between the adjacent semiconductor region 5a and semiconductor region 5b, and the adjacent semiconductor region 5b and semiconductor region 5c, via a gate insulation film 156 (see FIG. 13). Further, a gate electrode 152 is formed horizontally and extended between the semiconductor region 151 and semiconductor region 154 via a gate insulation film (not shown). The gate electrode 152 also serves as a transfer transistor control line 131 (see FIG. 11(b)).
In the examples of FIGS. 12 and 13, the transfer transistor 4 is constituted of the gate electrode 152, the semiconductor region 154, the semiconductor region 151 and the gate insulation film (not shown). The transfer transistor 4 utilizes the semiconductor region 151 of the photodiode 3 as a source region. In addition, the reset transistor 15 is constituted of the gate electrode 153a, the semiconductor regions 5a and 5b, the gate insulation film 156. The amplifying transistor 14 is constituted of the gate electrode 153b, the semiconductor regions 5b and 5c, the gate insulation film 156. The reset transistor 15 and the amplifying transistor 14 share the semiconductor region 5b. 
In FIG. 12, 155 denotes a wiring. The wiring 155 is connected to the semiconductor region 154, the semiconductor region 5a and the gate electrode 153b via a contact 156a. 
As shown in FIGS. 12 and 13, an element separation section is formed in a pixel. As the miniaturization of pixels in the MOS type solid-state image capturing apparatus in resent years, the element separation section is, in many cases, formed by using an STI (Shallow Trench Isolation) method, which forms a trench in a semiconductor substrate.
However, with regard to the element separation section (“STI element separation section” hereinafter) formed by the STI method, there is a problem of causing a crystal defect or stress defect near the element separation section. More particularly, a defect of white dots, namely a white defect, is observed on a playback screen if the crystal defect occurs in the MOS type solid-state image capturing apparatus. Although the number of the dots depends on the STI forming method and the size of the solid-state image capturing apparatus, the number ranges from several to several thousands. Further, when the stress defect occurs in the MOS type solid-state image capturing apparatus, an STI stress defect layer starts to generate a leak current flowing from the element separation section to the photodiode, so that a small and uneven irregularity is observed on a playback screen.
Among such defects, the local dot defect (white defect), which is due to the crystal defect, can be corrected with the advancement of the recent digital technology, so that the dot defect is not a major concern as before. However, it is difficult to correct the small and uneven irregularity by the digital processing due to the STI stress defect layer. This is because a memory with a large capacity is required to correct the irregularity that occurs on the entire screen, thereby increasing the cost of a system to correct the defect.
Therefore, it is proposed to implant an impurity, which has an opposite conductivity with that of a source drain region of the MOS transistor, into a forming region of the STI element separation section to provide an STI leak stopper (see Reference 1, for example). Reference 1 discloses an example of forming an STI leak stopper to surround a side and a bottom of an element separation section. When the STI leak stopper is provided, the leak current can be prevented from flowing from the element separation section to the photodiode, thereby preventing the uneven irregularity from appearing on a display screen.
Herein, the STI leak stopper disclosed in Reference 1 will be described with reference to FIG. 14.
FIG. 14 is a partial cross sectional view showing a manufacturing step of the conventional MOS type solid-state image capturing apparatus having the STI leak stopper formed therein, with FIGS. 14(a) to (d) showing a series of a major step. In FIGS. 14(a) to (d), the left half of the figures shows a pixel section A and the right half of the figures shows a peripheral circuit section B.
In general, both an N-channel MOS transistor and a P-channel MOS transistor are formed on a semiconductor substrate in the MOS type solid-state image capturing apparatus. In FIG. 14(a) to (d), however, only a region (NMOS region) for forming the N-channel MOS transistor is shown.
First, as shown in FIG. 14(a), a trench 701 for forming an STI element region is selectively formed in a forming region of the STI element separation section on the semiconductor substrate 100. Next, a resist film 702 having an opening on a pixel region A is formed, and an impurity is implanted obliquely using the resist film 702 as an ion implantation mask. As a result, an STI leak stopper 703 is formed along the side and the bottom of the trench 701. Herein, the semiconductor substrate 100 is an n-type silicon substrate. Further, a p-type impurity is implanted into the STI leak stopper 703, so that the p-type impurity also serves to separate the two photodiodes that is formed by the n-type impurity.
However, according to this ion implantation step, the p-type impurity is implanted into a region other than the forming region of the STI element separation section, namely, a forming region A1 of a photodiode and a forming region A2 of a transistor (readout transistor) for reading out a signal charge stored in a photodiode. Therefore, the impurity concentration of the well (see FIG. 14(b)) that is formed in the forming region A1 and the forming region A2 is greater than the impurity concentration of the well (see FIG. 14(b)) that is formed in the peripheral circuit section B.
Next, as shown in FIG. 14(b), after the resist film 702 is removed, an insulation, such as a silicon oxide film, is embedded in the trench 701 formed in the substrate described above to form an STI element separation section 704. Next, a resist film 705 is formed, the resist film having an opening on the transistor forming region A2 of the pixel section A and the peripheral circuit section B, and a p-type impurity is implanted obliquely using the resist film 705 as an ion implantation mask. As a result, a p-type well 706 is formed in the transistor forming region A2 of the pixel section A and the peripheral circuit section B.
Next, the p-type impurity is further ion-implanted using the resist film 705 as a mask. As a result, a channel region 707 of a transistor is formed in the transistor forming region A2 and the peripheral circuit section B. In addition, a threshold voltage Vth of a transistor can be controlled by adjusting the impurity concentration in the channel region 707.
Next, as shown in FIG. 14(c), after the resist film 705 is removed, a resist film 709, (shown with a dotted line) having an opening on a portion above the transistor forming region A1, is formed, and an n-type impurity is ion-implanted using the resist film 709 as a mask. As a result, an n-type semiconductor region 710 that constitutes a photodiode is formed. Note that the semiconductor region 710 can also be formed before the channel region 707 is formed.
Next, after the resist film 709 is removed, a gate insulation film 714 that is composed of a silicon oxide film is formed in the transistor forming region A2 and the peripheral circuit section B, and subsequently, a gate electrode 708 that is composed of polysilicon is formed on the insulation film 704.
Next, as shown in FIG. 14(d), forming and etching are performed on the insulation film, and a side wall insulation film (side wall spacer) 711 is formed on the sides of the gate insulation film 714 and the gate electrode 708. Next, a resist pattern 712, having an opening on a portion above the transistor forming region A2 and the peripheral circuit section B, is formed, and an n-type impurity is implanted using the resist pattern 712 as a mask. As a result, a source drain region 713 of a transistor is formed. Subsequently, an interlayer insulation film, various wirings, a microlens and the like are formed to complete the MOS type solid-state image capturing apparatus.
Whereas an n-type semiconductor region is arranged on the surface of the photodiode that constitutes the light receiving section in the solid-state image capturing apparatus disclosed in Reference 1, the conventional solid-state image capturing apparatus also includes a p-type semiconductor layer formed on the surface of the n-type semiconductor region so that an embedded photodiode is formed in the light receiving section.
According to the example shown in FIG. 14, the STI leak stopper 703 is formed, so that the leak current can be prevented from flowing from the element separation section 704 to the photodiode (semiconductor region 710). As a result, the uneven irregularity that appears on a display screen can be controlled.
However, the impurity concentration of the well formed in the pixel section increases if the leak stopper is formed near the element separation section. As a result, a back bias effect tends to occur in a transistor formed on a semiconductor substrate and the output characteristics of a source follower circuit in the MOS type solid-state image capturing apparatus decreases. An explanation with respect to such problems will be described below.
In general, one of the most important parameters in a MOSFET is a threshold voltage VT. An ideal threshold voltage VT can be given by an equation (1) below. In the equation (1) below, ∈s denotes a dielectric constant of silicon, q denotes a charge amount per one electron, NA denotes an impurity concentration of a semiconductor substrate, ψB denotes a Fermi level, and COX denotes a gate oxide film capacitance value.
                              V          T                =                                                            2                ⁢                                  ɛ                  S                                ⁢                                                      qN                    A                                    ⁡                                      (                                          2                      ⁢                                              φ                        B                                                              )                                                                                      C              OX                                +                      2            ⁢                          φ              B                                                          (        1        )            
In addition, In the MOSFET, the threshold voltage VT is influenced by a substrate bias voltage VBS. That is, when a voltage in a reverse direction is applied between the semiconductor substrate and the source, the width of the depletion layer is widened and the threshold voltage VT, which is necessary to cause an inversion, is increased. This is referred to a so called back bias effect. The threshold voltage VT can be expressed using the substrate bias voltage VBS by an equation (2) below. Note that VT0 is a threshold voltage when the VBS is 0 (zero).
                              V          T                =                              V                          T              ⁢                                                          ⁢              0                                +                                                                      2                  ⁢                                      ɛ                    S                                    ⁢                                      qN                    A                                                                              C                OX                                      ⁢                          (                                                                                          2                      ⁢                                              φ                        B                                                              +                                          V                      BS                                                                      -                                                      2                    ⁢                                          φ                      B                                                                                  )                                                          (        2        )            
Herein, the equation (2) described above can be expressed by an equation (4) below when γ is set as shown in an equation (3) below. In the equation (4), the voltage on the right-hand side expresses an error from the ideal output.
                    γ        =                                            2              ⁢                              ɛ                S                            ⁢                              qN                A                                                          C            OX                                              (        3        )                                                      V            T                    -                      V                          T              ⁢                                                          ⁢              0                                      =                  γ          ⁡                      (                                                                                2                    ⁢                                          φ                      B                                                        +                                      V                    BS                                                              -                                                2                  ⁢                                      φ                    B                                                                        )                                              (        4        )            
Further, FIG. 15 is a circuit diagram showing a circuit structure of a basic source follower circuit. The source follower circuit can be used with a low power supply voltage and has a characteristic of a fast response. The source follower circuit is commonly known as a level shift circuit. In FIG. 15, since a transistor MA is not grounded, the threshold voltage VT of the transistor MA is easily influenced by the back bias effect. Electric potentials Vin, VG and VOUT shown in FIG. 15 can be expressed by an equation (5) below using the equation (4) described above.Vin−Vout−VG=γ(√{square root over (2φB+Vout)}−√{square root over (2φB)})  (5)
Further, in the source follower circuit shown in FIG. 15, a voltage gain Av (=Vout/Vin) can be expressed by an equation (6) based on the equation (5) described above.
                              A          V                =                  1                      1            +                          γ                              2                ⁢                                                      2                    ⁢                                                                                            2                          ⁢                                                      φ                            B                                                                          +                                                  V                          out                                                                                                                                                                            (        6        )            
From the equation (6) described above, AV≈1 when the value for γ is small. In addition, from the equation (6) described above, the larger the value for γ, the linearity of the source follower circuit is further decreased and the voltage gain becomes smaller. Based on this fact, the linearity of the source follower circuit can be increased by decreasing the value for γ, In addition, the voltage gain can be increased by decreasing the value for γ, and therefore, the dynamic range of the MOS type solid-state image capturing apparatus can be expanded in the MOS type solid-state image capturing apparatus.
From the equation (3) described above, it is understood that an impurity concentration NA of the semiconductor substrate can be decreased so as to decrease the value for γ. Therefore, the output characteristics of the source follower circuit can be improved by diluting the concentration of the well formed in the pixel region.
However, as described above, the impurity concentration of the well formed in the pixel region increases if a leak stopper is formed near the element separation section. Therefore, it will be difficult to improve the linearity of the source follower circuit and to expand the dynamic range.
In order to solve such problems, a method for counter doping an impurity, which has the opposite conductivity with the conductivity of the well, directly under the gate of the output transistor, which constitutes the source follower circuit (see Reference 2, for example). According to the method disclosed in Reference 2, the linearity of the source follower circuit can be improved and the dynamic range can be expanded because the impurity concentration NA of the semiconductor substrate can be decreased. In addition, the variation of threshold voltage VT can be controlled because the impurity concentration can be decreased in the surface layer of the well. As a result, the back bias effect in the transistor can also be controlled.
Reference 1: Japanese Laid-Open Publication No. 2004-253729
Reference 2: Japanese Laid-Open Publication No. 2004-241638